Digital image sensors employ massive arrays of pixels. Each row of the array is read out sequentially, with the voltage signal from each of the individual pixels of the row output on parallel column bus lines. These signals are captured by an analog to digital converter and converted to digital values, which are typically stored in a temporary/volatile memory means such as an SRAM memory element. Subsequently, the stored data from the memory means is read out of the volatile memory means for further processing and/or durable storage.
Following analog to digital conversion, pixel output values comprising a series of bits are stored as separate “words” in the memory array, the words being a series of memory cells making up a column. Columns are read out sequentially. When a column is selected for readout, each of the cells in the column are read out simultaneously to a set of data buses which are in connection with an external device such as a signal processing or memory device. Between each readout of a column on the set of data buses, the bus lines are reset by application of a pre-charging voltage, to clear residual signal, reset the lines to a reference voltage, and improve signal resolution.
The alternating cycles of pre-charge and readout must be carefully timed. If readout overlaps with column pre-charging, there is a risk of a short circuit resulting from the pre-charge voltage being applied simultaneously with the memory cell output. In ideal operation, the pre-charging step is completed and the bus lines have settled to the reference voltage prior to the cell outputs from next column readout. However, in actual operation, delays address resolution, opening and closing of column selection gates, and other factors often lead to overlap between the pre-charging and readout steps, resulting in short circuits or “glitches.”
Accordingly, there is a need in the art to prevent short circuit glitches from occurring when reading out multiple columns of a SRAM or like memory device. The invention comprises a memory array readout scheme wherein an alternating series of parking intervals between each readout is utilized to take the readout circuitry completely off-line for a short time interval, allowing a clean transition from pre-charge step to readout step. During this period, the read-out circuitry is “parked” and inactive such that there is no connection to the external output during the pre-charging step and pre-charging signals can settle.
The novel parking scheme of the invention is enabled by the use of Gray code address inputs and a unique decoder configuration which takes the readout circuitry offline during the pre-charging step. In essence, the column readout signals are spaced every two or more counts of the input address generator to create the parking interval, as described below.